The subject matter of the present application relates to a microelectronic package including stacked microelectronic elements, and to methods of fabricating the package.
Microelectronic elements, such as semiconductor chips, are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the element itself. Microelectronic elements are typically packaged, optionally with substrates, to form microelectronic packages having terminals that are electrically connected to the element's contacts. The terminals of the package may then be connected to an external microelectronic component, such as a circuit panel.
It is desirable to package plural chips in a “stack” arrangement, i.e., where plural chips are placed one on top of another, to save space. In a stacked arrangement, several chips can be mounted to occupy a surface area, such as of a substrate, that is less than the total surface area of all the stacked chips. The reduced area of the stacked chips can result in very efficient utilization of area on a printed circuit board (“PCB”) to which the stacked chips can eventually be attached.
Further improvements are desirable in the art of producing multi-chip packages that can be connected with a microelectronic component external to the packages.